1. Field of the Invention
The present invention relates to a circuit device that has plural semiconductor circuit devices formed on independent substrates, respectively, and, more particularly to a circuit device, improvement of yield of which is realized.
2. Description of the Related Art
In recent years, advances in communication and storage devices are more remarkable than advances in semiconductors. According to the “Gilder's Law” proposed by George Gilder, a band width in communication increases at speed at least three times as high as an increase in an ability of computers. A capacity of an external storage increases at speed exceeding the “Moore's Law”.
On the other hand, the semiconductor manufacturing technique is becoming complicated year after year. For example, a phase shift mask method for correcting a limit of optical lithography, an immersion photoexposure device that immerses a semiconductor substrate in a liquid to process the semiconductor substrate, and the like have been introduced. Cost and time for creating masks have been exponentially increasing.
Whereas a circuit size formed on one semiconductor chip increases, circuit design becomes more and more difficult because of an increase in crosstalk between wirings. Thus, a design man-hour is steadily increasing. It is becoming difficult to entirely design one semiconductor chip from the beginning and it is becoming essential to reuse design resources.
In order to cope with the complication of the semiconductor manufacturing technique and the increase in a design man-hour, a semiconductor integrated circuit of a new structure called a Structured ASIC has been proposed. In the Structured ASIC, a circuit cell having a structure with rougher granularity than a basic gate such as a NAND circuit is used as a minimum unit of a circuit. Unlike an FPGA (field programmable gate array) and the like, a circuit having a desired function is formed by mask routing for customizing a part of wiring according to an application. Although the mask routing is inferior to a standard cell system in terms of an area, by using the mask routing, there is an advantage that waste is remarkably reduced compared with a reconfigurable wiring structure in the FPGA and it is possible to develop a semiconductor chip in a short time compared with the standard cell system.
As a representative thesis concerning a basic logical unit of the Structured ASIC, for example, there is “Regular logic fabrics for a via patterned gate array (VPGA), CMU K. Y. Tong, IBM R. Puri, IEEE 2003 Custom integrated circuits conference”. In this thesis, a basic unit is constituted by using a three-input lookup table, a scan flip-flop, two three-input NAND circuits, and seven buffers. When a layout using the contents of this basic unit and a layout by the standard cell system are compared, although an area in the former layout is larger than the latter layout by 40% to 68%, delays are substantially the same. In the U.S. Pat. No. 6,236,229, a logic cell in which a NAND circuit is connected to an input of a lookup table is proposed.
In order to realize reuse of design resources, it is a general practice to organize design data of functional blocks into a library as IPs (Intellectual Properties). Examples of means for connecting IP cores in a chip include an AXI bus proposed by ARM Limited in the United States and an OCP (Open Core Protocol) that is an on-chip bus protocol. In these buses, it is possible to feed different data flows and hang plural masters from an identical bus. Consequently, a mechanism for connecting a group of IP cores, which perform plural functions, to an identical bus and efficiently using the IP cores is proposed.